Area-Efficient Parallel Reconfigurable Stream Processor for Symmetric Cryptograph

Represented by application-specific instruction set processors (ASIPs) and array processors, existing cryptographic face challenges in application to mobile terminals with sensitive security requirements. Typically, ASIPs have limited computational efficiency algorithmic adaptability. An processor requires massive circuits perform fully expansive computations for ciphers, such are unaffordable terminals. To overcome these issues, we propose a highly area-efficient parallel reconfigurable symmetric cipher stream combining the characteristics of cryptograph stream-state processing advantages architectures. This has hierarchical architecture multi-dimensional parallelism. It decouples computation from data transmission, facilitating parallelism between algorithm operation scheduling. Furthermore, excavates vertical pipeline horizontal block its processes. Additionally, it takes multi-granular units reconfigures map different algorithms efficiently. These mechanisms significantly improve area intensity. The processor’s prototype was verified synthesised 65 nm CMOS process. Many typical ciphers were mapped onto processor. Experimental results demonstrate excellent performance feedback/no-feedback modes small (1.26 mm2). Therefore, is clearly higher than other better prospects future applications.